Recently, electronic equipment such as personal computers and mobile telephones is highly integrated and greater packaging density is realized, and pitch fine design of an electronic package which is mounted for such electronic equipment has been developed at the same time. As the integration and downsizing of the electronic package proceed, concerns about reliability of packaging components, in particular, a solder connection part are increased.
Generally speaking, when a high density packaging is required for an electronic packaging, BGA (Ball Grid Array) or CSP (Chip Scale Package) is widely used. However, a solder connection part of such an electronic package is exposed to stress such as temperature change and fall impact force. Thus, in order to apply such electronic package to actual products, it is necessary to perform sufficient evaluation about strength reliability.
Previously, as a solder connection part strength (micro connection part strength) evaluation, there is an evaluation method with a CAE (Computer Aided Engineering) system based on the simulation technology such as a finite-element method. Today, evaluation with this CAE system is required in design and development of a new package.
However, in the evaluation with the CAE system, when the strength evaluation of the whole electronic package is performed, creation of simulation model and mesh data and simulation calculation need a significant amount of time, because the construction of the electronic package is complicated. Thus, it might take several days to obtain simulation result.
Hence, there is a following technique for evaluating an electronic package (see the following patent document 1). In the technique, to decrease the time necessary for simulation, the analysis model of the electronic package is subjected to rough element division to perform outline analysis of the whole electronic package. On the basis of the result of the outline analysis, a target solder bump is extracted, and the analysis model of the extracted solder bump is subjected to fine (dense) element division to perform detail analysis, thereby the electronic package is evaluated.
[Patent Document 1] Japanese Patent application Laid-open No. 2000-99550